1. Field of the Invention
The present invention relates to a circuit and a method for generating multiphase clock signals and corresponding indication signals.
2. Description of the Related Art
Semiconductor memory devices are widely used in many electronic products and computer systems to store and retrieve data. Presently, semiconductor memory devices have become highly integrated and operate at higher speed to improve system performance. In order to enhance the operation speed of the semiconductor devices, a double data rate synchronous dynamic random access memory (DDR SDRAM) device has been developed to provide twice the operation speed of a conventional synchronous memory device. The DDR SDRAM allows data transfers on both the rising and falling edges of the system clock, and thus provides twice as much data as the conventional synchronous memory device.
As is known to one skilled in the art, the DDR SDRAM adopts a 2-bit prefetch operation to output 2-bit data to a data pad during one clock cycle. In order to prefetch more data bits, a DDR2 SDRAM and a DDR3 SDRAM have been developed. The DDR2 SDRAM adopts a 4-bit prefetch operation to output 4-bit data to a data pad during two clock cycles, and the DDR3 SDRAM adopts an 8-bit prefetch operation to output 8-bit data to a data pad during four clock cycles. As such, the data transfer rate of the DDR2 SDRAM and DDR3 SDRAM is improved by increasing the number of the prefetch bits.
In order to serially transfer parallel data to an output terminal of the memory device in an N-bit prefetch operation, a multiplexer is required during operation. FIG. 1 illustrates a conventional multiplexer 10 used in a 4-bit prefetch operation. Referring to FIG. 1, the multiplexer 10 includes a plurality of latches 102, 104, 106, and 108, and a plurality of switches 112, 114, 116, and 118.
The latches 102, 104, 106, and 108 simultaneously prefetch 4-bit data D0, D1, D2, and D3, which are transmitted from a memory cell array (not shown) via a data path, to the switches 112, 114, 116, and 118 in response to a control signal CTL. Thereafter, the switches 112, 114, 116, and 118 sequentially transfer data stored in the latches 102, 104, 106, and 108 to a node N1 in response to signals P1, P2, P3, and P4, wherein signals P1, P2, P3, and P4 are sequentially generated at a fixed interval.
FIG. 2 is an operational timing diagram illustrating operations of the conventional circuit of FIG. 1. Seventh signals are shown in FIG. 2, labeled XCLK (an external system clock signal), CTL, P1, P2, P3, P4, and DOUT (an output signal at an output terminal DQ).
The signals P1, P2, P3, and P4 are usually generated from an internal multiphase clock generation circuit (not shown). Therefore, a delay time Td occurs between rising edges of each of the multiphase signals P1, P2, P3, and P4 and rising edges of a corresponding one of the external clock signal XCLK because of internal capacitors and resistors. In FIG. 2, Td is controlled to be zero. In order to read data in synchronization with the rising edges and falling edges of the external clock signal XCLK, a corresponding indication signal is required of which timing is slightly earlier than that of the edges of the external clock signal XCLK. Therefore, there is need to develop new approaches to generate multiphase clock signals and corresponding indication signals which are suitable for use in the DDR SDRAM.